The present disclosure relates to a semiconductor circuit, and particularly to a voltage controlled oscillator circuit for low power applications.
The rapid growth of wireless communication systems such as global system for mobile communications (GSM), CDMA (code division multiple access), WCDMA (wideband code division multiple access), and 802.11a/b/g has driven the proliferation of high performance functional blocks to be integrated into low cost complementary metal oxide semiconductor (CMOS) devices. In multi-gigahertz range wireless communication, the communication bandwidth is heavily dependent on the quality of the signal source or frequency synthesizer that includes a voltage controlled oscillator (VCO).
The ever increasing requirement for the bandwidth places very stringent requirements on the design of a VCD in terms of frequency, power consumption, and noise level. At the same time, the next generation of communication chips will be integrated into a low cost deep submicron process. This means that the supply voltage for a VCO needs to be reduced with the ongoing scaling of CMOS devices. Thus, the next generation data signal modulator (DSM) design is expected to provide a reduced power supply voltage without phase noise degradation.
Usually, a complementary local oscillator (LO) VCO design is preferred by designers because of low phase noise and low power consumption. The disadvantage of the complementary LO VCO is high voltage headroom. Novel technology to simultaneously address low phase noise, low power consumption, and low voltage headroom is thus desired.